The present disclosure relates generally to semiconductor device manufacturing, and more particularly to the fabrication of the gate electrodes of field-effect transistors used within integrated circuits.
Very large scale integrated (VLSI) circuits using field effect transistors (FETs) commonly feature complimentary metal oxide silicon (CMOS) semiconductor components used within the circuits. Such CMOS circuits often require complimentary transistors, n-channel (NMOS) and p-channel (PMOS) type transistors located adjacent or in very close proximity to each other. These transistor types, NMOS and PMOS CMOS devices, are typically constructed with gate regions comprising a first layer containing a gate dielectric material such as silicon dioxide (SiO2). A second layer, the gate electrode, is located directly on the top of the first, typically comprised of doped silicon, such as poly-crystalline (poly) or amorphous silicon. The gate electrode, serves as a conducting electrode to the gate dielectric of the transistor. The doped silicon material of the gate electrode is often silicided with a metal film during subsequent device fabrication steps, to lower and improve the resistance of the transistors' gate connections.
The gate dielectric and electrode layers of both, NMOS and PMOS CMOS transistors are typically fabricated concurrently utilizing the same manufacturing process steps. The concurrent fabrication processes produce gate structures of similar material and thicknesses for the two transistor types. FIGS. 1A through 1D illustrate the typical process steps for the fabrication of the gate regions of CMOS transistors. FIG. 1A is a cross-sectional view of a silicon wafer substrate 100 after the fabrication of isolation structures upon the wafer. The silicon substrate 102 is shown with shallow trench isolation (STI) structures 104 fabricated into the wafer. The STI structures 104 function to electrically isolate individual or small groups of transistors from other individual or small groups of transistors. It is noted that these small groups of transistors may include a mix of both NMOS and PMOS transistors. The first layer of the gate region, the gate dielectric 106 is shown in FIG. 1B, having been grown on top of the silicon wafer substrate 100. The thickness of the gate dielectric 106, as grown, is very uniform and consistent throughout its area of growth. FIG. 1C shows the second gate layer, the gate electrode layer 108 after it's deposition on top of the gate dielectric layer 106. The deposited gate electrode layer 108 is also very uniform and consistent in thickness. The grown gate dielectric 106 and the deposited gate electrode layer 108 are subsequently patterned via photolithography and etched to create individual transistor gates. FIG. 1D illustrates the fabricated transistor gates after the photolithography pattern, etch and photoresist removal operations. There are individual transistor gates, each with their own separate gate dielectric layer 110 and gate electrode layer 112. It is noted that the thickness of the newly formed gate dielectric 110 and gate electrode 112 layers are approximately the same for all of the transistor gates.
The fact that the NMOS and PMOS transistors feature gate dielectric and electrodes thicknesses that are similar imposes some issues and difficulties for tuning and setting the transistors' electrical performances. Each transistor type, NMOS and PMOS, are transistors of different doping types, featuring different dopant type (n-type versus p-type) ions placed within their electrical transistor channels, under the gate dielectric. The different types of dopant ions exhibit differing property behaviors. One such behavior is the thermal diffusion coefficient, the property of thermally-induced dopant diffusion, or movement through the solid in which they are incorporated. Device and process designers may accommodate for the dopant diffusion differences by such techniques as adjusting the sizing of the individual transistors, in addition to adjusting the initial dopant levels and placements as they are incorporated. These transistor sizing and initial dopant-setting techniques are devised such that subsequent thermal operations induced upon the transistors allow the dopants to move and settle upon the desired, final levels and positions at the completion of the device fabrication processes.
The issues with dopant movement within the gate electrodes are more difficult to resolve. Dopant movement induced by the thermal processes may be tolerated by one transistor type while causing detrimental effects to the other. Specifically, these transistor issues may include dopant penetration, dopant depletion, and dopant inter-diffusion.
Dopant penetration occurs when dopants placed into the conducting gate electrode layer diffuses through the underlying gate oxide dielectric layer of the gate electrode to the transistor electrical channel of the semiconductor substrate. Such penetration may occur during the thermal operations for the semiconductor substrate wafers after the gate regions have already been fabricated. Such thermal processes may apply dopant diffusion temperatures between 400 and 1200 degrees Celsius. In addition, the transistors used within the advanced device and process technologies are even more susceptible to the dopant penetration issue. Such advanced transistors may have physical gate lengths of 65 nm or less and thin gate dielectric layers with 20 angstrom or less in thicknesses. The issue of dopant penetration may be lessened with a thicker gate electrode layer above the gate dielectric. Thicker gate electrode may allow the moving dopants to stay more within the layer, rather than penetrating thru the gate dielectric. However, for other design considerations, and the concerns with dopant depletion within the gate electrode layer, merely increasing gate electrode thickness may not be compatible or practical to implement.
Dopant depletion occurs when dopants placed into the gate conducting gate electrode are insufficiently distributed within the entire depth (thickness) of the layer. As result, there is a region of the gate poly-silicon electrode which is depleted of the desired dopant, enough to alter the desired electrical performance of the transistor. Subsequent post-gate thermal processes may not be sufficient to uniformly redistribute the non-uniform dopant. Post-gate thermal processes may even cause evenly distributed dopants to move enough to create a depleted region within the gate electrode layer. This issue of dopant depletion may be minimized or eliminated if the gate electrode used thickness was accommodating for the amount or dopant movement within the gate electrode layer. The gate electrode layer must be thick enough to minimize the previously discussed dopant penetration issue, while not being too thick to allow dopant depletion within the layer.
Dopant inter-diffusion relates to the cross-contamination of the transistor dopants between NMOS and PMOS transistors. The n-type dopants of the NMOS transistor may diffuse into the p-type doped areas and/or electrical channel of a PMOS transistor as well as the diffusion of p-type dopants into the n-type areas and/or electrical channel of an NMOS transistor. The issue of dopant inter-diffusion is strongly influenced by the proximities, and diffusion paths and distances between the opposing dopant regions. This issue of dopant inter-diffusion restricts and constrains the allowed thermal budgets applied upon the fabricated gate regions.
As new device and process technologies advance, transistor gates become geometrically smaller and thinner in size. The issues and problems associated with the dopant distribution and cross-contamination become more important as well as more difficult to overcome.
What is desired is an improved method for the fabrication of transistor gate regions such that the issues related to dopant distribution and cross-contamination are appropriately dealt with.